We report a 0.18 µm CMOS lab-on-a-chip system that monolithically integrates a passive radio frequency identification (RFID) interface and an 8 × 8 array of capacitance sensors configured for measuring the capacitance change resulting from an overlying biological specimen. This lab-on-CMOS platform is designed to operate wirelessly, first in a harvesting mode in which on-chip power is generated via the inductive coupling of an on-chip antenna to an external antenna, and second, in a sense-and-transmit mode where the capacitance sensor array is scanned and the measured data are transmitted to the external antenna using the same on-chip antenna. This paper presents characterization results of the passive RFID interface and of the sensor core, the latter utilizing several test analytes. The proposed system will facilitate the integration and packaging of a large number of chips in wet environments, paving the way for the inclusion of lab-on-CMOS technology in standard bio-analytical lab practice.

Accurate cell detection in time-lapse microscopy is essential for quantitative cell-based assays but remains challenging in settings with limited labeled data and time-varying image acquisition conditions. These challenges are particularly pronounced in perfusion-less lab-on-CMOS platforms, where long-duration bright-field imaging is used to establish ground truth for label-free electrical measurements and where experiment-specific artifacts such as focus drift induce domain shifts across time points. In this work, we formulate cell detection for lab-on-CMOS time-lapse microscopy as a transductive learning problem in which unlabeled target images of interest are available during training. We propose a two-stage transductive correlation-filter-based detection framework with pseudo-label adaptation. A source-domain correlation filter trained from a small labeled set is first used to generate region proposals on a target image, and high-confidence responses are treated as pseudo-labels to train an imagespecific correlation filter for refined classification. Experimental results in a lab-on-CMOS time-lapse dataset achieve AP50 scores of up to 0.87 and consistently outperform inductive baselines and classical correlation-based trackers that experience domain shift. These results demonstrate an annotation-efficient and scalable detection strategy tailored to lab-on-CMOS time-lapse microscopy.

Combinatorial optimization problems are central to science and engineering and specialized hardware from quantum annealers to classical Ising machines are being actively developed to address them. These systems typically sample from a fixed energy landscape defined by the problem Hamiltonian encoding the discrete optimization problem. The recently introduced Probabilistic Approximate Optimization Algorithm (PAOA) takes a different approach: it treats the optimization landscape itself as variational, iteratively learning circuit parameters from samples. Here, we demonstrate PAOA on a 64×64 perimeter-gated single-photon avalanche diode (pgSPAD) array fabricated in 0.35 μm CMOS, the first realization of the algorithm using intrinsically stochastic nanodevices. Each p-bit exhibits a device-specific, asymmetric (Gompertz-type) activation function due to dark-count variability. Rather than calibrating devices to enforce a uniform symmetric (logistic/tanh) activation, PAOA learns around device variations, absorbing residual activation and other mismatches into the variational parameters. On canonical 26-spin Sherrington-Kirkpatrick instances, PAOA achieves high approximation ratios with 2p parameters (p up to 17 layers), and pgSPAD-based inference closely tracks CPU simulations. These results show that variational learning can accommodate the non-idealities inherent to nanoscale devices, suggesting a practical path toward larger-scale, CMOS-compatible probabilistic computers.