We report on the breakdown characteristics of a single-photon avalanche diode structure fabricated in a 0.5 μm single-well CMOS process. This paper features two mechanisms for reducing perimeter breakdown. The first mechanism consists of using the lateral diffusion of adjacent n-wells to reduce the electric field at the diode's periphery, and the second makes use of a poly-silicon gate over the high field regions to modulate the electric field. We studied each technique independently as well as their combined effect on the devices' avalanche profiles. In addition to marked alterations in the current-voltage curves near and above breakdown, the diodes' breakdown voltages were increased by more than 4 V, indicating that perimeter breakdown was curtailed. We verified this assertion through a self-consistently solved 2-D numerical model based on Poisson's equation and the hole and electron current continuity equations coupled with rate equations for carrier generation due to impact ionization. The model revealed spatial maxima of the charge generation rates, thereby indicating regions susceptible to breakdown. Our investigation revealed that in native diodes, the generation rate peaked at the perimeter and near the junction's surface, suggesting perimeter breakdown. Conversely, in devices where suppression techniques were used, the region of maximum generation spread laterally and away from the surface, indicating full volumetric breakdown was achieved.