Characterization of single-photon avalanche diodes in standard CMOS
We report experimental results from a single-photon avalanche diode (SPAD) structure fabricated in a standard 0.5 μm single-well CMOS process. The diode consists of a p+/n-well junction, and its multiplication region is surrounded by a diffused guard-ring obtained through lateral diffusion of closely spaced n-wells. Moreover, a poly-silicon gate is placed over the junction's perimeter. These mechanisms help in curtailing perimeter breakdown, as has been previously reported. In this work, we study their combined effect on the junction's breakdown voltage, and on the dark count rate when the avalanche diode is operated in Geiger mode. Our results show that the poly-silicon gate and the diffused guard ring both increase the breakdown voltage with roughly similar efficacy. Furthermore, our results reveal that the dark count rate (DCR) is reduced by a factor of 7 when the gate potential is decreased below -16 V, indicating that the surface regions depleted by the field not only help in preventing edge breakdown but also contribute in reducing the device's noise floor.